Electrical Engineering and Computer Sciences - Ph.D. / Sc.D.
http://hdl.handle.net/1721.1/7660
2015-11-16T18:30:38ZComputational investigation of pathogen evolution
http://hdl.handle.net/1721.1/99858
Computational investigation of pathogen evolution
Sealfon, Rachel (Rachel Sima)
Pathogen genomes, especially those of viruses, often change rapidly. Changes in pathogen genomes may have important functional implications, for example by altering adaptation to the host or conferring drug resistance. Accumulated genomic changes, many of which are functionally neutral, also serve as markers that can elucidate transmission dynamics or reveal how long a pathogen has been present in a given environment. Moreover, systematically probing portions of the pathogen genome that are changing more or less rapidly than expected can provide important clues about the function of these regions. In this thesis, I (1) examine changes in the Vibrio cholerae genome shortly after the introduction of the pathogen to Hispaniola to gain insight into genomic change and functional evolution during an epidemic. I then (2) use changes in the Lassa genome to estimate the time that the pathogen has been circulating in Nigeria and in Sierra Leone, and to pinpoint sites that have recurrent, independent mutations that may be markers for lineage-specific selection. I (3) develop a method to identify regions of overlapping function in viral genomes, and apply the approach to a wide range of viral genomes. Finally, I (4) use changes in the genome of Ebola virus to elucidate the virus' origin, evolution, and transmission dynamics at the start of the outbreak in Sierra Leone.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.; Cataloged from PDF version of thesis.; Includes bibliographical references (pages 105-118).
2015-01-01T00:00:00ZUncertainty quantification for integrated circuits and microelectrornechanical systems
http://hdl.handle.net/1721.1/99855
Uncertainty quantification for integrated circuits and microelectrornechanical systems
Zhang, Zheng, Ph. D. Massachusetts Institute of Technology
Uncertainty quantification has become an important task and an emerging topic in many engineering fields. Uncertainties can be caused by many factors, including inaccurate component models, the stochastic nature of some design parameters, external environmental fluctuations (e.g., temperature variation), measurement noise, and so forth. In order to enable robust engineering design and optimal decision making, efficient stochastic solvers are highly desired to quantify the effects of uncertainties on the performance of complex engineering designs. Process variations have become increasingly important in the semiconductor industry due to the shrinking of micro- and nano-scale devices. Such uncertainties have led to remarkable performance variations at both circuit and system levels, and they cannot be ignored any more in the design of nano-scale integrated circuits and microelectromechanical systems (MEMS). In order to simulate the resulting stochastic behaviors, Monte Carlo techniques have been employed in SPICE-like simulators for decades, and they still remain the mainstream techniques in this community. Despite of their ease of implementation, Monte Carlo simulators are often too time-consuming due to the huge number of repeated simulations. This thesis reports the development of several stochastic spectral methods to accelerate the uncertainty quantification of integrated circuits and MEMS. Stochastic spectral methods have emerged as a promising alternative to Monte Carlo in many engineering applications, but their performance may degrade significantly as the parameter dimensionality increases. In this work, we develop several efficient stochastic simulation algorithms for various integrated circuits and MEMS designs, including problems with both low-dimensional and high-dimensional random parameters, as well as complex systems with hierarchical design structures. The first part of this thesis reports a novel stochastic-testing circuit/MEMS simulator as well as its advanced simulation engine for radio-frequency (RF) circuits. The proposed stochastic testing can be regarded as a hybrid variant of stochastic Galerkin and stochastic collocation: it is an intrusive simulator with decoupled computation and adaptive time stepping inside the solver. As a result, our simulator gains remarkable speedup over standard stochastic spectral methods and Monte Carlo in the DC, transient and AC simulation of various analog, digital and RF integrated circuits. An advanced uncertainty quantification algorithm for the periodic steady states (or limit cycles) of analog/RF circuits is further developed by combining stochastic testing and shooting Newton. Our simulator is verified by various integrated circuits, showing 10² x to 10³ x speedup over Monte Carlo when a similar level of accuracy is required. The second part of this thesis presents two approaches for hierarchical uncertainty quantification. In hierarchical uncertainty quantification, we propose to employ stochastic spectral methods at different design hierarchies to simulate efficiently complex systems. The key idea is to ignore the multiple random parameters inside each subsystem and to treat each subsystem as a single random parameter. The main difficulty is to recompute the basis functions and quadrature rules that are required for the high-level uncertainty quantification, since the density function of an obtained low-level surrogate model is generally unknown. In order to address this issue, the first proposed algorithm computes new basis functions and quadrature points in the low-level (and typically high-dimensional) parameter space. This approach is very accurate; however it may suffer from the curse of dimensionality. In order to handle high-dimensional problems, a sparse stochastic testing simulator based on analysis of variance (ANOVA) is developed to accelerate the low-level simulation. At the high-level, a fast algorithm based on tensor decompositions is proposed to compute the basis functions and Gauss quadrature points. Our algorithm is verified by some MEMS/IC co-design examples with both low-dimensional and high-dimensional (up to 184) random parameters, showing about 102 x speedup over the state-of-the-art techniques. The second proposed hierarchical uncertainty quantification technique instead constructs a density function for each subsystem by some monotonic interpolation schemes. This approach is capable of handling general low-level possibly non-smooth surrogate models, and it allows computing new basis functions and quadrature points in an analytical way. The computational techniques developed in this thesis are based on stochastic differential algebraic equations, but the results can also be applied to many other engineering problems (e.g., silicon photonics, heat transfer problems, fluid dynamics, electromagnetics and power systems). There exist lots of research opportunities in this direction. Important open problems include how to solve high-dimensional problems (by both deterministic and randomized algorithms), how to deal with discontinuous response surfaces, how to handle correlated non-Gaussian random variables, how to couple noise and random parameters in uncertainty quantification, how to deal with correlated and time-dependent subsystems in hierarchical uncertainty quantification, and so forth.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.; Cataloged from PDF version of thesis.; Includes bibliographical references (pages 155-168).
2015-01-01T00:00:00ZA continuous-time multi-stage noise-shaping delta-sigma modulator for next generation wireless applications
http://hdl.handle.net/1721.1/99854
A continuous-time multi-stage noise-shaping delta-sigma modulator for next generation wireless applications
Yoon, Do Yeon
A continuous-time (CT) delta-sigma ([delta][sigma]) modulator for modern wireless communication applications is investigated in this thesis. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function (NTF). In order to increase the effective order of the NTF, a 2-loop sturdy multi-stage noise-shaping (SMASH) architecture is utilized. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of the DT implementation. Furthermore, the proposed CT SMASH architecture provides a better quantization noise suppression capability than the DT SMASH architecture by more completely canceling the quantization noise from the first loop. The CT SMASH architecture is implemented with several circuit techniques suitable for high operation speed. These circuit techniques allow the proposed CT [delta][sigma] modulator to achieve wide bandwidth, high resolution, and low power consumption for modern wireless communication applications. As a result, the prototype fabricated in 28nm CMOS achieves DR of 85dB, peak SNDR of 74.9dB, SFDR of 89.3dBc and Schreier FOM of 172.9dB over a 50MHz bandwidth at a 1.8GHz sampling frequency.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.; Cataloged from PDF version of thesis.; Includes bibliographical references (pages 115-121).
2015-01-01T00:00:00ZFundamental limits of the switching abruptness of tunneling transistors
http://hdl.handle.net/1721.1/99853
Fundamental limits of the switching abruptness of tunneling transistors
Teherani, James Towfik
The tunneling field-effect transistor (TFET) is one of the most promising candidates for future low-power electronics because of its potential to achieve a subthreshold swing less than the 60 mV/decade thermal limit at room temperature. It can surpass this limit because the turn-on of tunneling does not sample the Maxwell-Boltzmann distribution of carriers that gives rise to the 60 mV/decade limit in conventional devices. However, theoretical predictions and experimental measurements of TFET device characteristics have differed by a wide margin-experimental subthreshold characteristics have not achieved the switching steepness (i.e., the change in drain current with applied gate voltage) of theoretical simulations. Non-ideal effects, such as non-abrupt band edges, phonon-assisted tunneling, and trap states, are discussed as mechanisms that may degrade theoretical predications. A strained-Si/strained-Ge bilayer TFET is used as a test-bed device to better understand the discrepancy between simulation and experiment. The bilayer TFET studied in this work eliminates channel doping and uses the strained-Si/strained-Ge heterostructure. Band-to-band tunneling occurs perpendicular to the gate, in-line with the gate electric field. Multiple gates are used so that the impact of the directionality of tunneling on switching abruptness can be studied. The band alignment of the strained-Si/strained-Ge heterostructure is extracted from a MOS-capacitor structure though an experimental quasistatic CV technique. The extracted effective band gap (related to the tunneling barrier) is shown to be only -200 meV for the heterostructure, and the valence band offset is shown to be -100 meV larger than predicted by density-functional theory. New deformation potentials are suggested for the Si-Ge material system based on the experimentally extracted band alignments. The impact of quantization on the turn-on voltage and gate-leakage current in a thin-body bilayer TFET structure is studied, and large confinement energy is shown to be especially problematic at body thicknesses less than 10 nm. An InAs structure with a body thickness less than 7 nm is shown to require a larger turn-on voltage than either Si or Ge homostructures due to the very light electron mass in InAs that leads to a large confinement energy. The strained- Si/strained-Ge heterostructure is shown to dramatically reduce the turn-on voltage due to its small effective band gap. Quantization is shown to limit the gate efficiency since increasing the body voltage, in order to align the electron and hole eigenstates in energy, increases the electric field across the structure, which in turn increases quantization. Gate leakage current increases exponentially as the body thickness decreases because the body voltage (and hence, the electric field) at turn-on increases with decreasing body thickness and gate leakage is exponentially dependent on the electric field. Non-ideal two-dimensional effects are investigated as mechanisms that degrade the switching characteristics of perpendicular TFETs (i.e. devices with tunneling perpendicular to the gate). Abrupt termination of a heavily doped semiconductor layer, often present in perpendicular TFET structures, can lead to large in-plane electric fields that give rise to parasitic diagonal tunneling paths, as opposed to the desired perpendicular tunneling paths. While the turn-on of each leakage path may be individually sharp, the sum of all tunneling paths is smeared by the multiple turn-ons and results in a degraded transfer characteristic for the device. The characteristic length, used for determining the length scale of potential fluctuations in short-channel MOSFETs, is suggested as a parameter that can be used to evaluate the likelihood of parasitic tunneling paths in a perpendicular TFET structure. The fabrication of the 3Gate strained-Si/strained-Ge bilayer TFET is detailed. The process includes epitaxial growth of a highly strained heterostructure, planarization of a bottom gate, wafer bonding of an epitaxial wafer to a handle wafer, etch-back of the epitaxial wafer leaving the thin strained-Si/strained-Ge heterostructure, and standard processing to create devices. Future work on electrical characterization of the experimental 3Gate bilayer TFET is discussed. Several test configurations are suggested as a way to probe the effects of diagonal tunneling on the abruptness of the switching characteristics.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.; Cataloged from PDF version of thesis.; Includes bibliographical references (pages 114-123).
2015-01-01T00:00:00Z