| dc.contributor.advisor |
Rohit Kapur and Daniel A. Spielman. |
en_US |
| dc.contributor.author |
Sitchinava, Nodari S. (Nodari Shalva), 1981- |
en_US |
| dc.contributor.other |
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. |
en_US |
| dc.date.accessioned |
2005-06-02T19:42:50Z |
|
| dc.date.available |
2005-06-02T19:42:50Z |
|
| dc.date.copyright |
2003 |
en_US |
| dc.date.issued |
2003 |
en_US |
| dc.identifier.uri |
http://hdl.handle.net/1721.1/18034 |
|
| dc.description |
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. |
en_US |
| dc.description |
Includes bibliographical references (p. 61-64). |
en_US |
| dc.description.abstract |
Fast developments in semiconductor industry have led to smaller and cheaper integrated circuit (IC) components. As the designs become larger and more complex, larger amount of test data is required to test them. This results in longer test application times, therefore, increasing cost of testing each chip. This thesis describes an architecture, named Dynamic Scan, that allows to reduce this cost by reducing the test data volume and, consequently, test application time. The Dynamic Scan architecture partitions the scan chains of the IC design into several segments by a set of multiplexers. The multiplexers allow bypassing or including a particular segment during the test application on the automatic test equipment. The optimality criteria for partitioning scan chains into segments, as well as a partitioning algorithm based on this criteria are also introduced. According to our experimental results Dynamic Scan provides almost a factor of five reduction in test data volume and test application time. More theoretical results reach as much as ten times the reductions compared to the classical scan methodologies. |
en_US |
| dc.description.provenance |
Made available in DSpace on 2005-06-02T19:42:50Z (GMT). No. of bitstreams: 2
57253435.pdf: 2707604 bytes, checksum: b084449e2a609c03f55ee72aedb9e726 (MD5)
57253435-MIT.pdf: 2713809 bytes, checksum: 754f4041028c47faa063a70e08bacdc5 (MD5)
Previous issue date: 2003 |
en |
| dc.description.statementofresponsibility |
by Nodari S. Sitchinava. |
en_US |
| dc.format.extent |
64 p. |
en_US |
| dc.format.extent |
2707604 bytes |
|
| dc.format.extent |
2713809 bytes |
|
| dc.format.mimetype |
application/pdf |
|
| dc.format.mimetype |
application/pdf |
|
| dc.language.iso |
eng |
en_US |
| dc.publisher |
Massachusetts Institute of Technology |
en_US |
| dc.rights |
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. |
en_US |
| dc.rights.uri |
http://dspace.mit.edu/handle/1721.1/7582 |
|
| dc.subject |
Electrical Engineering and Computer Science. |
en_US |
| dc.title |
Dynamic scan chains : a novel architecture to lower the cost of VLSI test |
en_US |
| dc.type |
Thesis |
en_US |
| dc.description.degree |
M.Eng. |
en_US |
| dc.contributor.department |
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. |
en_US |
| dc.identifier.oclc |
57253435 |
en_US |
