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Nano-scale scratching in chemical-mechanical polishing

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dc.contributor.advisor Jung-Hoon Chun and Nannaji Saka. en_US
dc.contributor.author Eusner, Thor en_US
dc.contributor.other Massachusetts Institute of Technology. Dept. of Mechanical Engineering. en_US
dc.date.accessioned 2008-11-07T19:06:36Z
dc.date.available 2008-11-07T19:06:36Z
dc.date.copyright 2008 en_US
dc.date.issued 2008 en_US
dc.identifier.uri http://hdl.handle.net/1721.1/43133
dc.description Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2008. en_US
dc.description Includes bibliographical references (leaves 125-127). en_US
dc.description.abstract During the chemical-mechanical polishing (CMP) process, a critical step in the manufacture of ultra-large-scale integrated (ULSI) semiconductor devices, undesirable nano-scale scratches are formed on the surfaces being polished. As the width of the interconnect Cu lines continues to shrink to below 60 nm, and as the traditional Si02 dielectric is replaced by the compliant, lowdielectric-constant materials, scratching has emerged as a challenging problem. This thesis presents a contact mechanics based approach for modeling nano-scale scratching by the hard abrasive particles in the slurry. Single-particle models that use elastic and plastic analyses to determine both the lower- and upper-bounds for the load per particle are introduced. These bounds are established for both homogenous and composite coatings. Multi-particle models are also presented. These models use contact mechanics at the pad-particle-coating interface to relate the global parameters of CMP, such as pressure, particle radius, slurry volume fraction and the material and geometrical properties of the pad and coating, to the widths and depths of scratches in the coatings. A lower- and upper-limit for the scratch width and depth in CMP is defined. Controlled indentation and scratching experiments have been conducted using a Hysitron TriboIndenter to validate the single-particle models. Based on these experiments, the upper-bound load per particle is used to predict the widths and depths of scratches in coatings. Furthermore, polishing experiments have been conducted using a CMP tool to validate the limits. The upper-limit for the semi-width of a scratch is equal to the product of the particle radius and the square root of the ratio of pad hardness to coating hardness. For a typical CMP pad and Cu coating, this upper-limit is one-fifth of the particle radius. Based on the models and the experiments, practical solutions for mitigating scratching in CMP, especially Cu CMP, are suggested. en_US
dc.description.statementofresponsibility by Thor Eusner. en_US
dc.format.extent 127 leaves en_US
dc.language.iso eng en_US
dc.publisher Massachusetts Institute of Technology en_US
dc.rights M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. en_US
dc.rights.uri http://dspace.mit.edu/handle/1721.1/7582 en_US
dc.subject Mechanical Engineering. en_US
dc.title Nano-scale scratching in chemical-mechanical polishing en_US
dc.title.alternative Nano-scale scratching in CMP en_US
dc.type Thesis en_US
dc.description.degree S.M. en_US
dc.contributor.department Massachusetts Institute of Technology. Dept. of Mechanical Engineering. en_US
dc.identifier.oclc 246708928 en_US


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