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A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

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A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier

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Author: Sinangil, Mahmut E.; Verma, Naveen; Chandrakasan, Anantha P.
Department: Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology Laboratories
Publisher: Institute of Electrical and Electronics Engineers
Date Issued: 2009-11
Abstract:
8T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9 mW and 46 μW [mu W] respectively.
URI: http://hdl.handle.net/1721.1/61622
Other Identifiers: INSPEC Accession Number: 11037122
ISBN: 978-1-4244-4433-5
Citation: Sinangil, M.E., N. Verma, and A.P. Chandrakasan. “A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier.” Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian. 2009. 225-228. © 2009, IEEE
Version: Final published version
Terms of Use: Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
Published As: http://dx.doi.org/10.1109/ASSCC.2009.5357219
Journal: IEEE Asian Solid-State Circuits Conference (A-SSCC)

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