A 9GHz injection locked loop optical clock receiver in 32-nm CMOS

Abstract

The bottleneck of multi-core processors performance will be the I/O, for both on-chip core-to-core I/0, and off-chip core-to-memory. Integrated silicon photonics can potentially provide high-bandwidth low-power signal and clock distribution for multicore processors, by exploiting wavelength-division multiplexing. This thesis presents the technology environment of the monolithic optical/electrical chip, and then focuses on how an optical method would look like for both source-synchronous link and for on-chip global clock distribution. The injection-locked loop clock receiver that suits this architecture breaks the bandwidth/sensitivity tradeoff, and a self-adjusting mechanism is added to increase robustness. The simulated receiver sensitivity is - 14dBm at 9GHz, consuming 77.14pW and generating jitter within 0. 15ps when locked onto a mode-locked laser clock source. The chip infrastructure and testing procedures are then presented, and lastly a truly integrated optical-electrical design flow is shown as well.