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Title:
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Zero-crossing detector based reconfigurable analog system |
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Author:
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Lajevardi, P; Chandrakasan, A; Hae-Seung Lee, A |
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Department:
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Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science |
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Publisher:
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Institute of Electrical and Electronics Engineers (IEEE) |
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Issue Date:
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2010-11 |
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Abstract:
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A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92mW at 50MSPS with ENOB of 8.02b and FOM of 150fJ/conversion-step. A third order Butterworth filter is also demonstrated. The chip is implemented in 65nm technology. |
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URI:
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http://hdl.handle.net/1721.1/72194
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ISSN:
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978-1-4244-8300-6 |
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Citation:
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Lajevardi, P, A Chandrakasan, and Hae-Seung Lee. “Zero-crossing Detector Based Reconfigurable Analog System.” 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 2010. 1–4. © Copyright 2010 IEEE |
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Version:
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Final published version |
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Terms of Use:
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. |
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Published as:
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http://dx.doi.org/10.1109/ASSCC.2010.5716604
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Journal:
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2010 IEEE Asian Solid State Circuits Conference (A-SSCC) |
