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A 0.077 to 0.168 nJ/bit/iteration Scalable 3GPP LTE Turbo Decoder with an Adaptive Sub-Block Parallel Scheme and an Embedded DVFS Engine

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dc.contributor.author Cheng, Chih-Chi
dc.contributor.author Tsai, Yi-Min
dc.contributor.author Chen, Liang-Gee
dc.contributor.author Chandrakasan, Anantha P.
dc.date.accessioned 2012-08-17T19:26:17Z
dc.date.available 2012-08-17T19:26:17Z
dc.date.issued 2010-09
dc.date.submitted 2010-09
dc.identifier.isbn 978-1-4244-5758-8
dc.identifier.issn 0886-5930
dc.identifier.uri http://hdl.handle.net/1721.1/72198
dc.description.abstract 3GPP LTE requires a 100 Mbps of peak bandwidth, and the instantaneous throughput demand changes with different applications. Fixed sub-block parallel turbo decoding scheme introduces bit-error rate (BER) performance drop when the block length is short. In this paper, an LTE turbo decoder implemented on a 0.66 mm2 die in a 65 nm CMOS technology is presented. An adaptive sub-block parallel (ASP) decoding scheme that improves the BER performance by up to 2.7 dB while maintaining the same parallelism is developed. A DVFS engine combining with an early-termination scheme is also developed. It generates the supply voltage and the clock rate that lead to the lowest energy consumption given the output bandwidth requirement. The measured energy consumption is 0.077~0.168 nJ per bit per iteration and 0.39~0.85 nJ per bit. en_US
dc.description.sponsorship Mediatek, Inc. Fellowship en_US
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en_US
dc.relation.isversionof http://dx.doi.org/10.1109/CICC.2010.5617396 en_US
dc.rights Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. en_US
dc.source IEEE en_US
dc.title A 0.077 to 0.168 nJ/bit/iteration Scalable 3GPP LTE Turbo Decoder with an Adaptive Sub-Block Parallel Scheme and an Embedded DVFS Engine en_US
dc.type Article en_US
dc.identifier.citation Chih-Chi Cheng et al. “A 0.077 to 0.168 nJ/bit/iteration Scalable 3GPP LTE Turbo Decoder with an Adaptive Sub-block Parallel Scheme and an Embedded DVFS Engine.” 2010 IEEE Custom Integrated Circuits Conference (CICC), 2010. 1–4. © Copyright 2012 IEEE en_US
dc.contributor.department Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science en_US
dc.contributor.approver Chandrakasan, Anantha P.
dc.contributor.mitauthor Chandrakasan, Anantha P.
dc.relation.journal 2010 IEEE Custom Integrated Circuits Conference (CICC) en_US
dc.identifier.mitlicense PUBLISHER_POLICY en_US
dc.eprint.version Final published version en_US
dc.type.uri http://purl.org/eprint/type/ConferencePaper en_US
dspace.orderedauthors Chih-Chi Cheng; Yi-Min Tsai; Liang-Gee Chen; Chandrakasan, Anantha P. en


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