Now showing items 1-9 of 9

    • A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems 

      Qazi, Masood; Amerasekera, Ajith; Chandrakasan, Anantha P. (Institute of Electrical and Electronics Engineers (IEEE), 2013-10)
      In order to realize a digital system with no distinction between “on” and “off,” the computational state must be stored in nonvolatile memory elements. If the energy cost and time cost of managing the computational state ...
    • A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems 

      Qazi, Masood; Chandrakasan, Anantha P.; Amerasekera, Ajith (Institute of Electrical and Electronics Engineers (IEEE), 2013-02)
      Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy and high-performance ...
    • A 4kb memory array for MRAM development 

      Qazi, Masood (Massachusetts Institute of Technology, 2007)
      The circuits for a A 4kb array of Magnetic Tunnel Junctions (MTJs) have been designed and fabricated in a 0:18¹m CMOS process with three levels of metal. Support circuitry for addressing, reading, writing, and test mode ...
    • A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS 

      Qazi, Masood; Stawiasz, Kevin; Chang, Leland; Chandrakasan, Anantha P. (Institute of Electrical and Electronics Engineers, 2010-02)
      An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low-voltage operation are addressed with ...
    • Circuit design for embedded memory in low-power integrated circuits 

      Qazi, Masood (Massachusetts Institute of Technology, 2012)
      This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the ...
    • Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems 

      Sinangil, Mahmut E.; Yip, Marcus; Qazi, Masood; Rithe, Rahul; Kwong, Joyce; e.a. (Institute of Electrical and Electronics Engineers (IEEE), 2012-08)
      Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This tutorial covers the main building blocks of a system implementation including digital ...
    • Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis 

      Qazi, Masood; Tikeka, Mehul; Dolecek, Lara; Shah, Devavrat; Chandrakasan, Anantha P. (Institute of Electrical and Electronics Engineers, 2010-04)
      The impact of process variation in deep-submicron technologies is especially pronounced for SRAM architectures which must meet demands for higher density and higher performance at increased levels of integration. Due to ...
    • Low-Swing Signaling on Monolithically Integrated Global Graphene Interconnects 

      Lee, Kyeong-Jae; Qazi, Masood; Kong, Jing; Chandrakasan, Anantha P. (Institute of Electrical and Electronics Engineers, 2010-10)
      In this paper, we characterize the performance of monolithically integrated graphene interconnects on a prototype 0.35-μm CMOS chip. The test chip implements an array of transmitter/receivers to analyze the end-to-end data ...
    • Technique for Efficient Evaluation of SRAM Timing Failure 

      Qazi, Masood; Tikekar, Mehul; Dolecek, Lara; Shah, Devavrat; Chandrakasan, Anantha P. (Institute of Electrical and Electronics Engineers (IEEE), 2012-09)
      This brief presents a technique to evaluate the timing variation of static random access memory (SRAM). Specifically, a method called loop flattening, which reduces the evaluation of the timing statistics in the complex ...