Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
Name
Peh_Approaching the theoretical.pdf
Size
1.33 MB
Format
Adobe PDF
Checksum (MD5)
a6e0027019210810e8c7238e3a8d2e8b
Author(s)
Park, Sunghyun
Krishna, Tushar
Chen, Chia-Hsin
Daya, Bhavya Kishor
Chandrakasan, Anantha P.
Peh, Li-Shiuan
Date Issued
June 2012
Journal
Proceedings of the 49th Annual Design Automation Conference (DAC '12)
Publisher
Association for Computing Machinery (ACM)
Citation
Sunghyun Park, Tushar Krishna, Chia-Hsin Chen, Bhavya Daya, Anantha Chandrakasan, and Li-Shiuan Peh. 2012. Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI. In Proceedings of the 49th Annual Design Automation Conference (DAC '12). ACM, New York, NY, USA, 398-405.
Version
Author's final manuscript
Abstract
In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how we approach these limits through a combination of microarchitecture and circuit techniques. Our 1.1V 1GHz NoC chip achieves 1-cycle router-and-link latency at each hop and energy-efficient router-level multicast support, delivering 892Gb/s (87.1% of the theoretical bandwidth limit) at 531.4mW for a mixed traffic of unicasts and broadcasts. Through this fabrication, we derive insights that help guide our research, and we believe, will also be useful to the NoC and multicore research community.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike 3.0
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1145/2228360.2228431
