RF power potential of 45 nm CMOS technology
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del Alamo_RF power.pdf
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Author(s)
Gogineni, Usha
del Alamo, Jesus A.
Putnam, Christopher
Date Issued
March 2010
Journal
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)
Publisher
Institute of Electrical and Electronics Engineers
Citation
Gogineni, U., J.A. del Alamo, and C. Putnam. “RF power potential of 45 nm CMOS technology.” Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on. 2010. 204-207. © 2010 Institute of Electrical and Electronics Engineers.
Version
Final published version
Abstract
This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with a peak power-added efficiency (PAE) of 70% at 1.1 V. The PAE and P[subscript out] decrease with increasing device width because of a decrease in the maximum oscillation frequency (f[subscript max]) for large width devices. The PAE also decreases with increasing frequency because of a decrease in gain as the operating frequency approaches f[subscript max]. The RF power performance of 45 nm devices is shown to be very similar to that of 65 nm devices.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/SMIC.2010.5422960
