Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications
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Author(s)
Tausif, Mohd
Jain, Abhinandan
Khan, Ekram
Hasan, Mohd
Date Issued
January 5, 2021
Publisher
Springer US
Version
Author's final manuscript
Abstract
Abstract
This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual sensor networks (VSN) or Internet of Multimedia Things (IoMT). The main feature of the proposed architecture is the novel data scanning technique that makes memory requirement independent of the image size. The proposed architecture needs only (30S) words of memory, where S is the number of parallel processing units and a critical path delay (CPD) equal to the delay of a multiplier (Tm). Furthermore, a multiplierless version of this architecture is also proposed which reduces the CPD to Ta
MIT Department
Massachusetts Institute of Technology. Media Laboratory
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1007/s11042-020-10258-0
