Implementation of H.264 Decoder in Bluespec SystemVerilog
Name
219733601-MIT.pdf
Description
Full printable version
Size
3.45 MB
Format
Adobe PDF
Checksum (MD5)
ce4f7526915a510e6dc605da76a469ab
Author(s)
Lin, Chun-Chieh
Advisor(s)
Arvind.
Date Issued
2007
Publisher
Massachusetts Institute of Technology
Abstract
In this thesis, I present a implementation of a H.264 decoder designed in Bluespec SystemVerilog, a high level hardware description language. This design is intended to serve both as a more understandable reference code, as well as a starting point for efficient hardware implementations. I illustrate this by modifying this initial design to meet a performance requirement of 720p at 60 frames per second.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 75).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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