Exploiting irregular parallelism to accelerate FPGA routing
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zhu-alanyzhu-meng-eecs-2024-thesis.pdf
Description
Thesis PDF
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821.73 KB
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Adobe PDF
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518f4c03aed9e867fbb942b53904066a
Author(s)
Zhu, Alan Y.
Advisor(s)
Sanchez, Daniel
Date Issued
September 2024
Publisher
Massachusetts Institute of Technology
Abstract
In the era of hardware specialization, field-programmable gate arrays (FPGAs) provide a promising platform for computer architects, combining the programmability of software with the speed and performance of hardware. Despite this, compiling hardware programs onto FPGAs can be incredibly time-consuming, making it hard to develop and iterate on complex FPGA programs. Of particular relevance is the routing phase, which takes a circuit’s technology-mapped netlist and routes its signals using the switches and wires present on a given FPGA architecture, often with a target of minimizing critical path delay. This optimization problem is known to be NP-hard, and existing algorithms for approximating it exhibit very little regular parallelism.
This thesis accelerates the routing phase of VTR 8.0, a commonly used, open-source research tool for FPGA CAD flow. We show that despite the lack of regular parallelism, routing still exhibits significant irregular parallelism. This parallelism can be exploited on parallel architectures that provide hardware support for ordered tasks and fine-grained speculation, such as the Swarm architecture. Using Swarm, we exploit the parallelism present at the core of VTR’s algorithm, achieving a 35.9x speedup on a single routing iteration of a large benchmark (cholesky_mc) on 256 cores.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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