Compiler auto-vectorization with imitation learning
Name
NeurIPS-2019-compiler-auto-vectorization-with-imitation-learning-Paper.pdf
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Published version
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335.03 KB
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Adobe PDF
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Author(s) • • • •
Mendis, C
Yang, C
Pu, Y
Amarasinghe, S
Carbin, M
Date Issued
December 2019
Journal
Advances in Neural Information Processing Systems
Citation
Mendis, C, Yang, C, Pu, Y, Amarasinghe, S and Carbin, M. 2019. "Compiler auto-vectorization with imitation learning." Advances in Neural Information Processing Systems, 32.
Version
Final published version
Abstract
© 2019 Neural information processing systems foundation. All rights reserved. Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector instruction sets which allow compilers to exploit fine-grained data level parallelism. To exploit this parallelism, compilers employ auto-vectorization techniques to automatically convert scalar code into vector code. Larsen & Amarasinghe (2000) first introduced superword level parallelism (SLP) based vectorization, which is a form of vectorization popularly used by compilers. Current compilers employ hand-crafted heuristics and typically only follow one SLP vectorization strategy which can be suboptimal. Recently, Mendis & Amarasinghe (2018) formulated the instruction packing problem of SLP vectorization by leveraging an integer linear programming (ILP) solver, achieving superior runtime performance. In this work, we explore whether it is feasible to imitate optimal decisions made by their ILP solution by fitting a graph neural network policy. We show that the learnt policy, Vemal, produces a vectorization scheme that is better than the well-tuned heuristics used by the LLVM compiler. More specifically, the learnt agent produces a vectorization strategy that has a 22.6% higher average reduction in cost compared to the LLVM compiler when measured using its own cost model, and matches the runtime performance of the ILP based solution in 5 out of 7 applications in the NAS benchmark suite.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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DOI of Published Version
https://papers.nips.cc/paper/2019/hash/d1d5923fc822531bbfd9d87d4760914b-Abstract.html