Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Name
MIT-LCS-TM-572.pdf
Size
247.64 KB
Format
Adobe PDF
Checksum (MD5)
a6958484e6c07d27e9b7404898b6d3d8
Author(s)
Lee, Walter
Barua, R.
Srikrishna, D.
Babb, Jonathan
Sarkar, V.
Amarasinghe, Saman
Agarwal, Anant
Date Issued
December 1997
Series/Report no.
MIT-LCS-TM-572
Abstract
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocessors are ill-suited to exploit such advances. Achieving a high level of parallelism at a reasonable clock speed requires distributing the processor resources - a trend already visible in the dual-register-file architecture of the Alpha 21264.
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