Methodology for analysis of TSV stress induced transistor variation and circuit performance
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yu-final-ISQED2012.pdf
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Author(s)
Yu, Li
Chang, Wen-Yao
Zuo, Kewei
Wang, Jean
Yu, Douglas
Boning, Duane S.
Date Issued
March 2012
Journal
Proceedings of the 2012 Thirteenth International Symposium on Quality Electronic Design (ISQED)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Yu, Li, Wen-Yao Chang, Kewei Zuo, Jean Wang, Douglas Yu, and Duane Boning. “Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance.” Thirteenth International Symposium on Quality Electronic Design (ISQED) (March 19-21, 2012), Santa Clara, California. IEEE. p.216-222.
Version
Author's final manuscript
Abstract
As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach.
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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DOI of Published Version
https://doi.org/10.1109/ISQED.2012.6187497
