Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-core NoCs
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Peh_Physical vs.pdf
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Author(s)
Chen, Chia-Hsin
Agarwal, Niket
Krishna, Tushar
Koo, Kyung-Hoae
Peh, Li-Shiuan
Date Issued
May 2010
Journal
International Symposium on Networks-on-Chip (ACM/IEEE).
Publisher
Institute of Electrical and Electronics Engineers
Citation
Chen, C.-H.O. et al. “Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs.” Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on. 2010. 173-180. © 2010, IEEE
Version
Final published version
Abstract
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an important design choice that affects how these networks scale. Most current on-chip networks use 2-D mesh topologies which do not scale due to their large diameter and energy inefficiency. To tackle the scalability problem of 2-D meshes, various physical express topologies and virtual express topologies have been proposed. In addition, recently proposed link designs like capacitively driven low-swing interconnects can help lower link power and latency, and can favor these bypass designs. In this work, we compare these two kinds of express topologies under realistic system constraints using synthetic network traffic. We observe that both express topologies help reduce low-load latencies. Virtual topologies help improve throughput whereas the physical express topologies give better performance-per-watt.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/NOCS.2010.26
