Garnet: A Detailed on-Chip Network Model inside a Full-System Simulator
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Peh_GARNET.pdf
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Author(s)
Agarwal, Niket
Krishna, Tushar
Peh, Li-Shiuan
Jha, Niraj K.
Date Issued
May 2009
Journal
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009. ISPASS 2009
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Agarwal, Niket et al. “GARNET: A Detailed On-chip Network Model Inside a Full-system Simulator.” IEEE International Symposium on Performance Analysis of Systems and Software, 2009. ISPASS 2009. 33–42. © Copyright 2009 IEEE
Version
Final published version
Abstract
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. The interconnect power was also insignificant compared to the transistor power. With uniprocessor designs providing diminishing returns and the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores has become a critical part of the design. Transistor miniaturization has led to high global wire delay, and interconnect power comparable to transistor power. CMP design proposals can no longer ignore the interaction between the memory hierarchy and the interconnection network that connects various elements. This necessitates a detailed and accurate interconnection network model within a full-system evaluation framework. Ignoring the interconnect details might lead to inaccurate results when simulating a CMP architecture. It also becomes important to analyze the impact of interconnection network optimization techniques on full system behavior. In this light, we developed a detailed cycle-accurate interconnection network model (GARNET), inside the GEMS full-system simulation framework. GARNET models a classic five-stage pipelined router with virtual channel (VC) flow control. Microarchitectural details, such as flit-level input buffers, routing logic, allocators and the crossbar switch, are modeled. GARNET, along with GEMS, provides a detailed and accurate memory system timing model. To demonstrate the importance and potential impact of GARNET, we evaluate a shared and private L2 CMP with a realistic state-of-the-art interconnection network against the original GEMS simple network. The objective of the evaluation was to figure out which configuration is better for a particular workload. We show that not modeling the interconnect in detail might lead to an incorrect outcome. We also evaluate Express Virtual Channels (EVCs), an on-ch- ip network flow control proposal, in a full-system fashion. We show that in improving on-chip network latency-throughput, EVCs do lead to better overall system runtime, however, the impact varies widely across applications.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/ISPASS.2009.4919636
