The Parallel Persistent Memory Model
Name
PMM.pdf
Description
Accepted version
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754.81 KB
Format
Adobe PDF
Checksum (MD5)
fa7a4a1e49dfcacc5564c54a904758ff
Author(s)
Blelloch, Guy E
Gibbons, Phillip B
Gu, Yan
McGuffey, Charles
Shun, Julian
Date Issued
2018
Journal
Annual ACM Symposium on Parallelism in Algorithms and Architectures
Publisher
Association for Computing Machinery (ACM)
Version
Author's final manuscript
Abstract
© 2018 Association for Computing Machinery. We consider a parallel computational model, the Parallel Persistent Memory model, comprised of P processors, each with a fast local ephemeral memory of limited size, and sharing a large persistent memory. The model allows for each processor to fault at any time (with bounded probability), and possibly restart. When a processor faults, all of its state and local ephemeral memory is lost, but the persistent memory remains. This model is motivated by upcoming non-volatile memories that are nearly as fast as existing random access memory, are accessible at the granularity of cache lines, and have the capability of surviving power outages. It is further motivated by the observation that in large parallel systems, failure of processors and their caches is not unusual. We present several results for the model, using an approach that breaks a computation into capsules, each of which can be safely run multiple times. For the single-processor version we describe how to simulate any program in the RAM, the external memory model, or the ideal cache model with an expected constant factor overhead. For the multiprocessor version we describe how to efficiently implement a work-stealing scheduler within the model such that it handles both soft faults, with a processor restarting, and hard faults, with a processor permanently failing. For any multithreaded fork-join computation that is race free, write-after-read conflict free and has W work, D depth, and C maximum capsule work in the absence of faults, the scheduler guarantees a time bound on the model of OPWA + DPPAjlog1/(Cf) Wk in expectation, where P is the maximum number of processors, PA is the average number, and f ≤ 1/(2C) is the probability a processor faults between successive persistent memory accesses. Within the model, and using the proposed methods, we develop efficient algorithms for parallel prefix sums, merging, sorting, and matrix multiply.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/3210377.3210381
