An electrical-level superposed-edge approach to statistical serial link simulation
Name
Tsuk-2009-An electrical-level superposed-edge approach to statistical serial link simulation.pdf
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1.19 MB
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Checksum (MD5)
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Author(s)
Tsuk, Michael
Dvorscak, Daniel
Ong, Chin Siong
White, Jacob K.
Date Issued
December 2009
Journal
IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, 2009
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Tsuk, M. et al. "An electrical-level superposed-edge approach to statistical serial link simulation." IEEE, 2009. 717-724. © Copyright 2009 IEEE
Version
Final published version
Abstract
rute-force simulation approaches to estimating serial-link bit-error rates (BERs) become computationally intractable for the case when BERs are low and the interconnect electrical response is slow enough to generate intersymbol interference that spans dozens of bit periods. Electrical-level statistical simulation approaches based on superposing pulse responses were developed to address this problem, but such pulse-based methods have difficulty analyzing jitter and rise/fall asymmetry. In this paper we present a superposing-edge approach for statistical simulation, as edge-based methods handle rise/fall asymmetry and jitter in straightforward way. We also resolve a key problem in using edge-based approaches, that edges are always correlated, by deriving an efficient inductive approach for propagating the edge correlations. Examples are presented demonstrating the edge-based method's accuracy and effectiveness in analyzing combinations of uniform, Gaussian, and periodic distributed random jitter.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5361218
