Circuits for high-performance low-power VLSI logic
Name
133104456-MIT.pdf
Description
Full printable version
Size
22.22 MB
Format
Adobe PDF
Checksum (MD5)
f55c1c6f5d10ac0c064b98f2be8f5f5b
Author(s)
Ma, Albert
Advisor(s)
Krste Asanović.
Alternative Title
Circuits for high-performance low-power very large scale integration of circuits logic
Date Issued
2006
Publisher
Massachusetts Institute of Technology
Abstract
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 85-88).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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