Puppetmaster: a certified hardware architecture for task parallelism
Name
PerezLopez-arpl-meng-eecs-2021-thesis.pdf
Description
Thesis PDF
Size
402.87 KB
Format
Adobe PDF
Checksum (MD5)
ef3a6b1333696c65762d6d02d4638480
Author(s)
Perez-Lopez, Áron Ricardo
Advisor(s)
Chlipala, Adam
Date Issued
September 2021
Publisher
Massachusetts Institute of Technology
Abstract
This thesis presents Puppetmaster, a hardware accelerator for transactional workloads. Existing software and hardware frameworks for transactional memory and online transaction processing are not able to scale to hundreds or thousands of cores unless the rate of conflicts between transactions is very low. Puppetmaster aims to improve upon the scalability of concurrency control by requiring transactions to declare their read and write sets in advance and uses this information to only run transactions concurrently when they are known not to conflict. In this thesis, I present and evaluate the design of Puppetmaster in a high-level model, in cycle-accurate simulations, and on real reconfigurable hardware.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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