Reconfigurable processor for energy-scalable computational photography
Name
Computational Photography - ISSCC 2013.pdf
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9.18 MB
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Author(s)
Rithe, Rahul
Raina, Priyanka
Ickes, Nathan J.
Chandrakasan, Anantha P.
Tenneti, Srikanth V.
Date Issued
February 2013
Journal
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Rithe, R., P. Raina, N. Ickes, S. V. Tenneti, and A. P. Chandrakasan. “Reconfigurable Processor for Energy-Scalable Computational Photography.” 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (February 2013).
Version
Author's final manuscript
Abstract
Computational photography applications, such as lightfield photography, enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering form a significant part of computational photography. These techniques have a wide range of applications, including High-Dynamic Range (HDR) imaging, Low-Light Enhanced (LLE) imaging, tone management and video enhancement. The high computational complexity of such multimedia processing applications necessitates fast hardware implementations to enable real-time processing. This paper describes a hardware implementation of a reconfigurable multi-application processor for computational photography.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/ISSCC.2013.6487683
