An FPGA implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
Name
416591138-MIT.pdf
Description
Full printable version
Size
12.5 MB
Format
Adobe PDF
Checksum (MD5)
79b9b1a378f97c8dea297df4432942f8
Author(s)
Yamhure, Alessandro
Advisor(s)
Arvind.
Alternative Title
Field-programmable gate array implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
Date Issued
2008
Publisher
Massachusetts Institute of Technology
Abstract
This thesis describes the design, construction and integration of a multicore processor and a memory subsystem. The work is part of a joint project with IBM Watson research. The processors have multithreading capacities and implement the PowerPC ISA. The memory system consists of a parameterizable hierarchy of caches and random access memory units. All implementation was done in Bluespec System Verilog hardware synthesis language for placement on FPGA. Furthermore, this document analyzes the main tradeoffs and major challenges involved in building and integrating such a system.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 52).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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reproduction or distribution in any format is prohibited without written
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