A comparative evaluation of high-level hardware synthesis using Reed-Solomon decoder
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Arvind-A Comparative.pdf
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Author(s)
Agarwal, Abhinav
Ng, Man Cheuk
Mithal, Arvind
Date Issued
July 2010
Journal
IEEE Embedded Systems Letters
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Agarwal, Abhinav, Man Cheuk Ng, and Arvind. “A Comparative Evaluation of High-Level Hardware Synthesis Using Reed-Solomon Decoder.” IEEE Embedded Systems Letters 2.3 (2010): 72–76. © Copyright 2010 IEEE
Version
Final published version
Abstract
Using the example of a Reed-Solomon decoder, we provide insights into what type of hardware structures are needed to be generated to achieve specific performance targets. Due to the presence of run-time dependencies, sometimes it is not clear how the C code can be restructured so that a synthesis tool can infer the desired hardware structure. Such hardware structures are easy to express in an HDL. We present an implementation in Bluespec, a high-level HDL, and show a 7.8× improvement in performance while using only 0.45× area of a C-based implementation.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/LES.2010.2055231
