Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects
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Joshi-2009-Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects.pdf
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Author(s) • •
Joshi, Ajay J.
Kim, Byungsub
Stojanovic, Vladimir Marko
Date Issued
September 2009
Journal
17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009.
Publisher
Institute of Electrical and Electronics Engineers
Citation
Joshi, A., B. Kim, and V. Stojanovic. “Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects.” High Performance Interconnects, 2009. HOTI 2009. 17th IEEE Symposium on. 2009. 3-12. © Copyright 2010 IEEE
Version
Final published version
Abstract
In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, we explore the design of energy-efficient low-diameter networks (flattened butterfly and Clos) using equalized on-chip interconnects. These low-diameter networks are attractive as they can potentially provide uniformly high throughput and low latency across various traffic patterns, but require efficient global communication channels. In our case study, for a 64-tile system, the use of equalization for the wire channels in low-diameter networks provides 2x reduction in power with no loss in system performance compared to repeater-inserted wire channels. The use of virtual channels in routers further reduces the power of the network by 25-50% and wire area by 2x.
Subjects
on-chip network
multicore system
low power
equalized interconnects
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/HOTI.2009.13