A high performance zero-crossing based pipelined analog-to-digital converter
Name
276947916-MIT.pdf
Description
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3.3 MB
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Author(s)
Chu, Yue Jack
Advisor(s)
Hae-Seung Lee.
Date Issued
2008
Publisher
Massachusetts Institute of Technology
Abstract
In this thesis, I describe a zero-crossing based pipelined ADC. Unlike traditional pipelined ADCs, this work does not use any op-amps in the signal path. The use of zero-crossing based circuits made it possible to achieve a much better figure of merit. The ADC is design to operate at 200MS/s with a resolution of 12 bits. The simulated results suggest that the target performance is achievable with less than 10 mW of power. This design's figure of merit is at least an order of magnitude better than any existing designs that have comparable speed and accuracy performance. The design will be fabricated later to be tested in silicon.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (leaves 46-47).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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