An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS
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CICC2017_manuscript.pdf
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Author(s)
Biswas, Avishek
Arslan, Umut
Hamzaoglu, Fatih
Chandrakasan, Anantha P
Date Issued
July 2017
Journal
IEEE Custom Integrated Circuits Conference (CICC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Biswas, Avishek et al. "An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS." IEEE Custom Integrated Circuits Conference (CICC), April-May 2017, Austin, Texas, USA, IEEE Custom Integrated Circuits Conference (CICC), July 2017. © 2017 IEEE
Version
Author's final manuscript
Abstract
This paper presents a low-offset read sensing scheme for resistive memories. Due to increasing device variations in sub-32 nm CMOS processes, it becomes very challenging to design a high yield and low-offset read-sensing scheme. In this work we address these issues by using a pseudo-differential sensing scheme to get 2× signal margin and by full offset cancellation of the sense-amplifier, making it more suitable to tolerate variation from the memory array due to storage device resistance variation. Measurement results show the sense-amplifier can work with a 20mV input, which makes it ideal for small-signal sensing for resistive memories.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/cicc.2017.7993689
