Performance analysis of ultra-scaled InAs HEMTs
Name
Kharche-2009-Performance analysis of ultra-scaled InAs HEMTs.pdf
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936.38 KB
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Author(s)
del Alamo, Jesus A.
Kim, Dae-Hyun
Kharche, Neerav
Luisier, Mathieu
Date Issued
March 2010
Journal
2009 IEEE International Electron Devices Meeting (IEDM)
Publisher
Institute of Electrical and Electronics Engineers
Citation
Kharche, N. et al. “Performance analysis of ultra-scaled InAs HEMTs.” Electron Devices Meeting (IEDM), 2009 IEEE International. 2009. 1-4. © 2010 Institute of Electrical and Electronics Engineers.
Version
Final published version
Abstract
The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental Id-Vgs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yet-fabricated 20 nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage.
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/IEDM.2009.5424315
