Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation
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banshee.pdf
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Accepted version
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Author(s) • • • •
Yu, Xiangyao
Hughes, Christopher J.
Satish, Nadathur
Mutlu, Onur
Devadas, Srinivas
Date Issued
October 2017
Publisher
Association for Computing Machinery (ACM)
Citation
Yu, Xiangyao, Hughes, Christopher J., Satish, Nadathur, Mutlu, Onur and Devadas, Srinivas. 2017. "Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation."
Version
Author's final manuscript
Abstract
© 2017 Association for Computing Machinery. Placing the DRAM in the same package as a processor enables several times higher memory bandwidth than conventional offpackage DRAM. Yet, the latency of in-package DRAM is not appreciably lower than that of off-package DRAM. A promising use of in-package DRAM is as a large cache. Unfortunately, most previous DRAM cache designs optimize mainly for cache hit latency and do not consider bandwidth efficiency as a first-class design constraint. Hence, as we show in this paper, these designs are suboptimal for use with in-package DRAM. We propose a new DRAM cache design, Banshee, that optimizes for both in-package and off-package DRAM bandwidth efficiency without degrading access latency. Banshee is based on two key ideas. First, it eliminates the tag lookup overhead by tracking the contents of the DRAM cache using TLBs and page table entries, which is efficiently enabled by a new lightweight TLB coherence protocol we introduce. Second, it reduces unnecessary DRAM cache replacement traffic with a new bandwidth-aware frequency-based replacement policy. Our evaluations show that Banshee significantly improves performance (15% on average) and reduces DRAM traffic (35.8% on average) over the best-previous latency-optimized DRAM cache design.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1145/3123939.3124555