Instruction-Level Execution Migration
Name
MIT-CSAIL-TR-2010-019.pdf
Size
2.35 MB
Format
Adobe PDF
Checksum (MD5)
2315a0194d61e9585cc9c160cca00680
Author(s)
Devadas, Srinivas
Lis, Mieszko
Khan, Omer
Advisor(s)
Srini Devadas
Date Issued
April 17, 2010
Series/Report no.
MIT-CSAIL-TR-2010-019
Abstract
We introduce the Execution Migration Machine (EM²), a novel data-centric multicore memory system architecture based on computation migration. Unlike traditional distributed memory multicores, which rely on complex cache coherence protocols to move the data to the core where the computation is taking place, our scheme always moves the computation to the core where the data resides. By doing away with the cache coherence protocol, we are able to boost the effectiveness of per-core caches while drastically reducing hardware complexity. To evaluate the potential of EM² architectures, we developed a series of PIN/Graphite-based models of an EM² multicore with 64 x86 cores and, under some simplifying assumptions (a timing model restricted to data memory performance, no instruction cache modeling, high-bandwidth fixed-latency interconnect allowing concurrent migrations), compared them against corresponding directory-based cache-coherent architecture models. We justify our assumptions and show that our conclusions are valid even if our assumptions are removed. Experimental results on a range of SPLASH-2 and PARSEC benchmarks indicate that EM2 can significantly improve per-core cache performance, decreasing overall miss rates by as much as 84% and reducing average memory latency by up to 58%.
Persistent DSpace Link
