Logic characteristics of 40 nm thin-channel InAs HEMTs
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del Alamo-Logic characteristics.pdf
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Author(s)
Kim, Tae-Woo
Kim, Dae-Hyun
del Alamo, Jesus A.
Date Issued
July 2010
Journal
2010 International Conference on Indium Phosphide & Related Materials
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Kim, Tae-Woo, Dae-Hyun Kim, and Jesus A. del Alamo. “Logic Characteristics of 40 Nm Thin-channel InAs HEMTs.” 2010 International Conference on Indium Phosphide & Related Materials. IEEE, 2010. 1–4. © Copyright 2010 IEEE
Version
Final published version
Abstract
We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t[subscript ch] = 5 nm and we have compared them against, InAs HEMTs with t[subscript ch] = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. L[subscript g] = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and I[subscript ON]/I[subscript OFF] = 2.5 × 104, all at V[subscript DS] = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower f[subscript T] when compared with InAs HEMTs with t[subscript ch] = 10 nm.
MIT Department
Massachusetts Institute of Technology. Microsystems Technology Laboratories
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DOI of Published Version
https://doi.org/10.1109/ICIPRM.2010.5516257
