Designing a processor in Bluespec
Name
60678546-MIT.pdf
Description
Full printable version
Size
2.37 MB
Format
Adobe PDF
Checksum (MD5)
b4a611e151aa25a332f87d001641b970
Author(s)
Dave, Nirav Hemant, 1982-
Advisor(s)
Arvind.
Date Issued
2005
Publisher
Massachusetts Institute of Technology
Abstract
In this thesis, we designed a 2-way out-of-order processor in Bluespec implementing the MIPS I integer ISA. A number of scheduling optimizations were then used to bring the initial design up to the same level of cycle-level concurrency as found in standard RTL-level designs. From this, a general design methodology is proposed to effectively express, debug, and optimize large Bluespec designs.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 67).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Persistent DSpace Link
