Charge Storage Mechanism and Size Control of Germanium Nanocrystals in a Tri-layer Insulator Structure of a MIS Memory Device
Name
AMMNS004.pdf
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776.38 KB
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Checksum (MD5)
1ab1241f7186cb8437580f3aa5e7f5e9
Author(s)
Teo, L.W.
Ho, Van Tai
Tay, M.S.
Lei, Y.
Choi, Wee Kiong
Chim, Wai Kin
Antoniadis, Dimitri A.
Fitzgerald, Eugene A.
Date Issued
January 2003
Series/Report no.
Advanced Materials for Micro- and Nano-Systems (AMMNS);
Abstract
A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix.
Subjects
Ge nanocrystal
floating gate
metal-insulator-semiconductor
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