Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
Name
MIT-CSAIL-TR-2010-058.pdf
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726.3 KB
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Adobe PDF
Checksum (MD5)
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Author(s)
Kinsy, Michel
Pellauer, Michael
Advisor(s)
Srini Devadas
Date Issued
December 8, 2010
Series/Report no.
MIT-CSAIL-TR-2010-058
Abstract
Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. Each processing node has a 7-stage pipeline, fully bypassed, microprocessor running the MIPS-III ISA, a 4-stage input-buffer, virtual-channel router, and a local variable-size shared memory. Our design is highly modular with clear interfaces between the core, the memory hierarchy, and the on-chip network. In the baseline design, the microprocessor is attached to two caches, one instruction cache and one data cache, which are oblivious to the global memory organization. The memory system in Heracles can be configured as one single global shared memory (SM), or distributed shared memory (DSM), or any combination thereof. Each core is connected to the rest of the network of processors by a parameterized, realistic, wormhole router. We show different topology configurations of the system, and their synthesis results on the Xilinx Virtex-5 LX330T FPGA board. We also provide a small MIPS cross-compiler toolchain to assist in developing software for Heracles.
Subjects
Multicore Architecture Design
FPGA
Shared-Memory
Distributed Shared Memory
Network-on-Chip
RISC
MIPS
Virtual Channel
Wormhole Router
NoC Routing Algorithm
Terms of Use
Creative Commons Attribution 3.0 Unported
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