Self-Improvement for Circuit-Analysis Problems
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3618260.3649723.pdf
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713.92 KB
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Adobe PDF
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Author(s)
Williams, R. Ryan
Date Issued
June 10, 2024
Publisher
ACM
Citation
Williams, R. Ryan. 2024. "Self-Improvement for Circuit-Analysis Problems."
Version
Final published version
Abstract
Many results in fine-grained complexity reveal intriguing consequences from solving various SAT problems even slightly faster than exhaustive search. We prove a “self-improving” (or “bootstrapping”) theorem for Circuit-SAT, #Circuit-SAT, and its fully-quantified version: solving one of these problems faster for “large” circuit sizes implies a significant speed-up for “smaller” circuit sizes. Our general arguments work for a variety of models solving circuit-analysis problems, including non-uniform circuits and randomized models of computation.
We derive striking consequences for the complexities of these problems, in both the fine-grained and parameterized setting. For example, we show that certain fine-grained improvements on the runtime exponents of polynomial-time versions of Circuit-SAT would imply subexponential-time algorithms for Circuit-SAT on 2o(n)-size circuits, refuting the Exponential Time Hypothesis. We also show that any algorithm for Circuit-SAT with k inputs and n gates running in 1000000k + n1+ε time (for all ε > 0) would imply algorithms running in time (1+ε)k + n1+ε time (for all ε > 0), also refuting the Exponential Time Hypothesis. Applying our ideas in the #Circuit-SAT setting, we prove new unconditional lower bounds against uniform circuits with symmetric gates for functions in deterministic linear time.
Description
STOC ’24, June 24–28, 2024, Vancouver, BC, Canada
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1145/3618260.3649723
