Floorplacement for Partial Reconfigurable FPGA-Based Systems
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Montone-2011-Floorplacement for Partial Reconfigurable FPGA-Based Systems.pdf
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825.21 KB
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Author(s)
Montone, A.
Santambrogio, Marco Domenico
Redaelli, F.
Sciuto, D.
Date Issued
2011
Journal
International Journal of Reconfigurable Computing
Publisher
Hindawi
Citation
Montone, A. et al. “Floorplacement for Partial Reconfigurable FPGA-Based Systems.” International Journal of Reconfigurable Computing 2011 (2011) : 1-12. Copyright © 2011 A. Montone et al.
Version
Final published version
Abstract
We presented a resource- and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using
an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional Units that
are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities,
and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task
graphs with many externally connected RRs show lower improvement. The proposed approach results, as also demonstrated in
the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven
approaches and a highly increased probability of reuse of existing links (90% reduction can be obtained in the best case).
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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Creative Commons Attribution
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DOI of Published Version
https://doi.org/10.1155/2011/483681
