Repository logo
Log in(current)
Repository logoMIT Open ScholarshipDSpace@MIT
  1. Home
  2. MIT Open Access Articles
  3. MIT Open Access Articles
  4. Simulated Co-Optimization of Crystalline Silicon Solar Cell Throughput and Efficiency Using Continuously Ramping Phosphorus Diffusion Profiles

Simulated Co-Optimization of Crystalline Silicon Solar Cell Throughput and Efficiency Using Continuously Ramping Phosphorus Diffusion Profiles

Thumbnail Image
Download
Name

Buonassisi_Simulated co-optimization.pdf

Size

340.01 KB

Format

Adobe PDF

Checksum (MD5)

bd6dab8a5d17705fc8054e8134c3bf4b

Author(s)
Morishige, Ashley Elizabeth
•
Fenning, David P.
•
Hofstetter, Jasmin
•
Powell, Douglas Michael
•
Buonassisi, Tonio
Date Issued
June 2012
Journal
Proceedings of the 38th IEEE Photovoltaic Specialists Conference (PVSC), 2012
Publisher
Institute of Electrical and Electronics Engineers
Citation
Morishige, Ashley E. et al. “Simulated Co-optimization of Crystalline Silicon Solar Cell Throughput and Efficiency Using Continuously Ramping Phosphorus Diffusion Profiles.” 2012 38th IEEE Photovoltaic Specialists Conference (PVSC), IEEE, 2012. 002213–002217. CrossRef. Web.
Version
Author's final manuscript
Abstract
Defect engineering is essential for the production of high-performance silicon photovoltaic (PV) devices with cost-effective solar-grade Si input materials. Phosphorus diffusion gettering (PDG) can mitigate the detrimental effect of metal impurities on PV device performance. Using the Impurity-to-Efficiency (I2E) simulator, we investigate the effect of gettering temperature on minority carrier lifetime while maintaining an approximately constant sheet resistance. We simulate a typical constant temperature plateau profile and an alternative “volcano” profile that consists of a ramp up to a peak temperature above the typical plateau temperature followed by a ramp down with no hold time. Our simulations show that for a given PDG process time, the “volcano” produces an increase in minority carrier lifetime compared to the standard plateau profile for as-grown iron distributions that are typical for multicrystalline silicon. For an initial total iron concentration of 5×1013 cm-3, we simulate a 30% increase in minority carrier lifetime for a fixed PDG process time and a 43% reduction in PDG process cost for a given effective minority carrier lifetime while achieving a constant sheet resistance of 100 Ω/□.
Description
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6318036
MIT Department
Massachusetts Institute of Technology. Department of Mechanical Engineering
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike 3.0
http://creativecommons.org/licenses/by-nc-sa/3.0/
Persistent DSpace Link
http://hdl.handle.net/1721.1/78338
DOI of Published Version
https://doi.org/10.1109/PVSC.2012.6318036
Repository logo
PrivacyPermissionsAccessibilityContact us
Repository logo
Notify us about copyright concerns.