ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration
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Author(s) • • •
Kahng, Andrew B.
Li, Bin
Peh, Li-Shiuan
Samadi, Kambiz
Date Issued
April 2009
Journal
Design, Automation & Test in Europe Conference and Exhibition, DATE'09
Publisher
IEEE Computer Society
Citation
Kahng, Andrew B. et al. "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration." Design, Automation & Test in Europe Conference and Exhibition, DATE'09, 20-24 April, 2009, Nice France.
Version
Author's final manuscript
Abstract
As industry moves towards many-core chips, networks-on-chip
(NoCs) are emerging as the scalable fabric for interconnecting
the cores. With power now the first-order design constraint, earlystage
estimation of NoC power has become crucially important.
ORION [29] was amongst the first NoC power models released,
and has since been fairly widely used for early-stage power estimation
of NoCs. However, when validated against recent NoC
prototypes – the Intel 80-core Teraflops chip and the Intel Scalable
Communications Core (SCC) chip – we saw significant deviation
that can lead to erroneous NoC design choices. This
prompted our development of ORION 2.0, an extensive enhancement
of the original ORION models which includes completely
new subcomponent power models, area models, as well as improved
and updated technology models. Validation against the
two Intel chips confirms a substantial improvement in accuracy
over the original ORION. A case study with these power models
plugged within the COSI-OCC NoC design space exploration
tool [23] confirms the need for, and value of, accurate early-stage
NoC power estimation. To ensure the longevity of ORION 2.0,
we will be releasing it wrapped within a semi-automated flow that
automatically updates its models as new technology files become
available.
Description
conference website
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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