Cycle-accurate modeling of multicore processors on FPGAs
Name
868822166-MIT.pdf
Description
Full printable version
Size
16.4 MB
Format
Adobe PDF
Checksum (MD5)
b0ec3d97356503ccf69f3f20bbcc3e7f
Author(s)
Khan, Asif I. (Asif Imtiaz)
Advisor(s)
Arvind.
Date Issued
2013
Publisher
Massachusetts Institute of Technology
Abstract
We present a novel modeling methodology which enables the generation of a high-performance, cycle-accurate simulator from a cycle-level specification of the target design. We describe Arete, a full-system multicore processor simulator, developed using our modeling methodology. We provide details on Arete's resource-efficient and high-performance implementation on multiple FPGA platforms, and the architectural experiments performed using it. We present clear evidence that the use of simplified models in architectural studies can lead to wrong conclusions. Through two experiments performed using both cycle-accurate and simplified models, we show that on one hand there are substantial quantitative and qualitative differences in results, and on the other, the results match quite well.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 169-176).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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