Formal Verification of Hardware Synthesis
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Chlipala_Formal verification.pdf
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215.47 KB
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Author(s)
Braibant, Thomas
Chlipala, Adam
Date Issued
July 2013
Journal
Computer Aided Verification
Publisher
Springer-Verlag
Citation
Braibant, Thomas, and Adam Chlipala. “Formal Verification of Hardware Synthesis.” Lecture Notes in Computer Science (2013): 213–228.
Version
Original manuscript
Abstract
We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design.
Description
Original manuscript: January 21, 2013
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1007/978-3-642-39799-8_14
