Jenga: Software-Defined Cache Hierarchies
Name
2017.isca.jenga.pdf
Description
Accepted version
Size
1.68 MB
Format
Adobe PDF
Checksum (MD5)
9a8e740c53684378047b6eea80836326
Author(s)
Tsai, Po-An
Beckmann, Nathan Zachary
Sanchez, Daniel
Date Issued
June 2017
Journal
Computer Architecture News
Publisher
Association for Computing Machinery (ACM)
Citation
Tsai, Po-An et al. “Jenga: Software-Defined Cache Hierarchies.” Paper in the Computer Architecture News, 45, 2, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), June 24-28, 2017, Toronto, ON, Canada, Association for Computing Machinery (ACM) © 2017 The Author(s)
Version
Author's final manuscript
Abstract
Caches are traditionally organized as a rigid hierarchy, with multiple levels of progressively larger and slower memories. Hierarchy allows a simple, fixed design to benefit a wide range of applications, since working sets settle at the smallest (i.e., fastest and most energy-efficient) level they fit in. However, rigid hierarchies also add overheads, because each level adds latency and energy even when it does not fit the working set. These overheads are expensive on emerging systems with heterogeneous memories, where the differences in latency and energy across levels are small. Significant gains are possible by specializing the hierarchy to applications. We propose Jenga, a reconfigurable cache hierarchy that dynamically and transparently specializes itself to applications. Jenga builds virtual cache hierarchies out of heterogeneous, distributed cache banks using simple hardware mechanisms and an OS runtime. In contrast to prior techniques that trade energy and bandwidth for performance (e.g., dynamic bypassing or prefetching), Jenga eliminates accesses to unwanted cache levels. Jenga thus improves both performance and energy efficiency. On a 36-core chip with a 1 GB DRAM cache, Jenga improves energy-delay product over a combination of state-of-the-art techniques by 23% on average and by up to 85%.
MIT Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
Terms of Use
Creative Commons Attribution-Noncommercial-Share Alike
Persistent DSpace Link
DOI of Published Version
https://doi.org/10.1145/3140659.3080214
