Energy efficient ultra-wideband radio transceiver architectures and receiver circuits
Name
228658295-MIT.pdf
Description
Full printable version
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9.51 MB
Format
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Checksum (MD5)
e4b5221d251d6fdea5ba0029d6b4fadd
Author(s)
Lee, Fred S. (Fred Shung-Neng), 1979-
Advisor(s)
Anantha P. Chandrakasan.
Alternative Title
Energy efficient UWB radio transceiver architectures and receiver circuits
Date Issued
2007
Publisher
Massachusetts Institute of Technology
Abstract
Energy efficient short-range radios have become an active research area with proliferation of portable electronics. A critical specification for radio efficiency is energy/bit. The FCC has allocated the 3.1-10.6 GHz band for radios using ultra-wideband (UWB) signals. In this research, I exploit UWB signaling to develop energy efficient hardware systems for high and low data rate radios. In the high rate regime, a modular discrete prototype receiver is developed to observe pulsed UWB signals. Verification of system non-idealities upon bit-error-rate (BER) are easily observed with this system. The results are leveraged in designing a 3.1-10.6 GHz front-end in a 0.18 pm SiGe BiCMOS process, featuring an unmatched LNA and 802.11a switchable notch filter for interference mitigation. A 100 Mbps system demo is implemented to realize a wireless link. In the low rate regime, energy/bit increases because fixed power costs are less effectively amortized over fewer bits/sec. However, by using UWB PPM signaling, the receiver is duty-cycled so that energy/bit is decoupled from data rate. Through careful signaling, system, and circuit co-design, a non-coherent, 0-16.7 Mbps receiver is implemented in a 90 nm CMOS process with a 0.5 V and 0.65 V power supply. This work achieves 2.5 nJ/bit of energy efficiency over three orders of magnitude in data rate. With adjustable bandpass filters and a new relative compare demodulator, the receiver achieves 10-3 BER with -99 dBm sensitivity at 100 kbps. A first-pass acquisition algorithm is developed on an FPGA platform and a transceiver system demo is assembled using this chip.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 113-123).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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