Stealth dicing characterization, optimization, integration, and operations management for ultra-thin stacked memory dies
Name
921432746-MIT.pdf
Description
Full printable version
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29.22 MB
Format
Adobe PDF
Checksum (MD5)
f74178c480059e584fdbf6759aab4a46
Author(s)
Teh, Weng Hong
Advisor(s)
Roy Welsch and Duane Boning.
Date Issued
2014
Publisher
Massachusetts Institute of Technology
Abstract
This dissertation presents original work in the development of multi-strata subsurface infrared (1.342 [mu]m) nanosecond pulsed laser die singulation (stealth dicing) to enable defect-free ultra-thin stacked memory dies. The over-arching contribution is the first comprehensive and systematic experimental study of stealth dicing, encompassing process physics and simulation, characterization, optimization, and integration, as well as operations management, including statistical process control, sensitivities, interactions, and risk analysis. This work exploits the multi-strata interactions between generated thermal shockwaves and the preceding dislocation layers formed to initiate controlled crack fractures that separate the individual dies from within the interior of the wafer as a method for significant singulation-related defect reduction and die strength enhancement. A new partial-stealth dicing before grinding (p-SDBG) integration based upon the tandem use of three-strata stealth dicing followed by static loading from backgrinding to complete full kerf separation has successfully demonstrated defect-free eight die stacks of 25 and 46 [mu]m thick 2D NAND memory dies on high backside reflectance wafers for the first time. This work resulted in a 3.5% mean increase in memory/system test yield and has been used to realize production-worthy 64 GB retail memory products after passing reliability tests. Based on unit loadings at SanDisk Shanghai for 2014, this translates to annual cost savings averaging $12.OM when extending this technology to all systems-in-package (SIP) products consisting of 4-, 8-, and 16-die stacks.
Description
Thesis: M.B.A., Massachusetts Institute of Technology, Sloan School of Management, 2014. In conjunction with the Leaders for Global Operations Program at MIT.
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. In conjunction with the Leaders for Global Operations Program at MIT.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 191-197).
Subjects
Sloan School of Management.
Electrical Engineering and Computer Science.
Leaders for Global Operations Program.
MIT Department
Leaders for Global Operations Program at MIT
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Sloan School of Management
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