(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
Name
227033826-MIT.pdf
Description
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3.93 MB
Format
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Checksum (MD5)
402e027b274a4709d0895b8a12e52277
Author(s)
Kam, Brandon Ray
Advisor(s)
Stephen D. Wyatt and Michael H. Perrott.
Alternative Title
Jitter measurement built-in self-test circuit for phase locked loops
Date Issued
2005
Publisher
Massachusetts Institute of Technology
Abstract
This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 77-79).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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