Circuit-Aware System Design Techniques for Wireless Communication
Name
Everest Huang TR709.pdf
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2.55 MB
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Author(s)
Huang, Everest Wang
Date Issued
June 29, 2006
Series/Report no.
Technical Report (Massachusetts Institute of Technology, Research Laboratory of Electronics);
709
Abstract
When designing wireless communication systems, many hardware details are hidden
from the algorithm designer, especially with analog hardware. While it is difficult for
a designer to understand all aspects of a complex system, some knowledge of circuit
constraints can improve system performance by relaxing design constraints. The
specifications of a circuit design are generally not equally difficult to meet, allowing
excess margin in one area to be used to relax more difficult design constraints.
We first propose an uplink/downlink architecture for a network with a multiple
antenna central server. This design takes advantage of the central server to allow the
nodes to achieve multiplexing gain by forming virtual arrays without coordination, or
diversity gain to decrease SNR requirements. Computation and memory are offloaded
from the nodes to the server, allowing less complex, inexpensive nodes to be used.
We can further use this SNR margin to reduce circuit area and power consumption,
sacrificing system capacity for circuit optimization. Besides the more common trans-
mit power reduction, large passive analog components can be removed to reduce chip
area, and bias currents lowered to save power at the expense of noise figure. Given the
inevitable crosstalk coupling of circuits, we determine the minimum required crosstalk
isolation in terms of circuit gain and signal range. Viewing the crosstalk as a static
fading channel, we derive a formula for the asymptotic SNR loss, and propose phase
randomization to reduce the strong phase dependence of the crosstalk SNR loss.
Because the high peak to average power (PAPR) that results from multicarrier
systems is difficult for analog circuits to handle, the result is low power efficiencies.
We propose two algorithms, both of which can decrease the PAPR by 4 dB or more,
resulting in an overall power reduction by over a factor of three in the high and low
SNR regimes, when combined with an outphasing linear amplifier.
Description
Thesis Supervisor: Gregory W. Wornell
Title: Professor
MIT Department
Massachusetts Institute of Technology. Research Laboratory of Electronics
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