Zero-crossing detector based reconfigurable analog system
Name
Chandrakasan-Zero-crossing detector.pdf
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499.56 KB
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Author(s)
Lajevardi, Payam
Chandrakasan, Anantha P.
Lee, Hae-Seung
Date Issued
November 2010
Journal
2010 IEEE Asian Solid State Circuits Conference (A-SSCC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Lajevardi, P, A Chandrakasan, and Hae-Seung Lee. “Zero-crossing Detector Based Reconfigurable Analog System.” 2010 IEEE Asian Solid State Circuits Conference (A-SSCC), 2010. 1–4. © Copyright 2010 IEEE
Version
Final published version
Abstract
A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92mW at 50MSPS with ENOB of 8.02b and FOM of 150fJ/conversion-step. A third order Butterworth filter is also demonstrated. The chip is implemented in 65nm technology.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.
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DOI of Published Version
https://doi.org/10.1109/ASSCC.2010.5716604
