A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications
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Author(s)
Huang, Chao-Tsung
Tikekar, Mehul
Juvekar, Chiraag Shashikant
Sze, Vivienne
Chandrakasan, Anantha P.
Date Issued
February 2013
Journal
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Chao-Tsung Huang, M. Tikekar, C. Juvekar, V. Sze, and A. Chandrakasan. “A 249Mpixel/s HEVC Video-Decoder Chip for Quad Full HD Applications.” 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (February 2013).
Version
Author's final manuscript
Abstract
The latest video coding standard High Efficiency Video Coding (HEVC) provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents an integrated circuit which supports Quad Full HD (QFHD, 3840×2160) video decoding for the HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a two-stage sub-pipeline for memory optimization; 2) unified processing engines to address the hierarchical coding structure and many prediction and transform block sizes in area-efficient ways; 3) a motion compensation (MC) cache which reduces DRAM bandwidth for the LCU and meets the high throughput requirements which are due to the long filters.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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Creative Commons Attribution-Noncommercial-Share Alike
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DOI of Published Version
https://doi.org/10.1109/ISSCC.2013.6487682
