Automatic application-specific optimizations under FPGA memory abstractions
Name
1006384698-MIT.pdf
Description
Full printable version
Size
28.72 MB
Format
Adobe PDF
Checksum (MD5)
c2e6dcfe7891971fa8e283070b3d4e37
Author(s)
Yang, Hsin-Jung
Advisor(s)
Srinivas Devadas and Joel Emer.
Date Issued
2017
Publisher
Massachusetts Institute of Technology
Abstract
FPGA-based accelerators have great potential to achieve better performance and energy-efficiency compared to general-purpose solutions because FPGAs permit the tailoring of hardware to a particular application. This hardware malleability extends to FPGA memory systems: unlike conventional processors, in which the memory system is fixed at design time, cache algorithms and network topologies of FPGA memory hierarchies may all be tuned to improve application performance. As FPGAs have grown in size and capacity, FPGA physical memories have become richer and more diverse in order to support the increased computational capacity of FPGA fabrics. Using these resources, and using them well, has become commensurately more difficult, especially in the context of legacy designs ported from smaller, simpler FPGA systems. This growing complexity necessitates automated build procedures that can make good use of memory resources by performing resource-aware, application-specific optimizations. In this thesis, we leverage the freedom of abstraction to build program-optimized memory hierarchies on behalf of the user, making FPGA programming easier and more efficient. To enable better generation of these memory hierarchies, we first provide a set of easy-to-use memory abstractions and perform several optimization mechanisms under the abstractions to construct various memory building blocks with different performance and cost tradeoffs. Then, we introduce a program introspection mechanism to analyze the runtime memory access characteristics of a given application. Finally, we propose a feedback-directed memory compiler that automatically synthesizes customized memory hierarchies tailored for different FPGA applications and platforms, enabling user programs to take advantage of the increasing memory capabilities of modern FPGAs.
Description
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 159-167).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
Persistent DSpace Link
