A 4kb memory array for MRAM development
Name
220933302-MIT.pdf
Description
Full printable version
Size
2.08 MB
Format
Adobe PDF
Checksum (MD5)
b2069865e02e61b55f9a6e644a8eb19d
Author(s)
Qazi, Masood
Advisor(s)
John K. DeBrosse and Anantha P. Chandrakasan.
Alternative Title
Four kilobyte memory array for Magnetic Random Access Memory development
Date Issued
2007
Publisher
Massachusetts Institute of Technology
Abstract
The circuits for a A 4kb array of Magnetic Tunnel Junctions (MTJs) have been designed and fabricated in a 0:18¹m CMOS process with three levels of metal. Support circuitry for addressing, reading, writing, and test mode probing enables the characterization of the switching of a thin-film ferromagnetic layer in the MTJs. Specifically, novel mechanisms involving spin-transfer or thermal assistance can be studied and compared to current MRAM designs that switch the MTJ with current-induced magnetic fields. Using this array design, both high speed digital and quasi-static dI/dV experiments can be conducted to investigate the nature of the MTJ resistance hysteresis and process variation in addition to the switching behavior under both polarities of current.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 129-131).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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